The present invention relates to a phase sync circuit, or more in particular to a magnetic disk apparatus in which the write data transfer speed is changed in accordance with the inner and outer track of a magnetic disk.
In conventional apparatuses, a phase sync circuit for generating a sync clock is normally configured of a PLL (Phase-Locked Loop). Constants indicating the responsiveness of the PLL or phase sync circuit include a characteristic frequency W.sub.n and an attenuation rate .xi.. These constants are dependent on such conditions as the initial phase difference and the phase pull-in time.
The phase pull-in time changes with the data transfer speed if the pattern length is fixed, since the phase pull-in is requied to be effected within a phase sync pattern. If a PLL is configured with the gain of the frequency-phase comparator plus charge pump as K.sub.d and the gain of a VCO (voltage-controlled oscillator) as K.sub.o, the characteristic frequency W.sub.n and the attenuation rate .xi. are expressed as ##EQU1## where C.sub.1, C.sub.2 and R designate capacitors and a resistor respectively making up a filter.
In a conventional phase sync circuit for the information processing system, the data transfer speed is determined uniquely for each system. Once the data transfer speed of a system is determined, therefore, it is possible to calculate the most suitable constant for a PLL and set the same constant as a fixed value.
A magnetic disk unit for the information processing system, on the other hand, generally has a fixed write data speed. In such a case, however, the limitation of the linear recording density of the magnetic disk is determined by the innermost track, the density of which is progressively decreased toward the outer track.
A conventional phase sync circuit is well known as disclosed in JP-A-63-217719.
A configuration of this phase sync circuit is shown in FIG. 22.
The phase sync circuit comprises a phase comparator 121 for comparing an input pulse signal with the phase of the output signal of a voltage controlled oscillator, a smoothing filter 112 for smoothing the output of the phase comparator, a loop filter 113 connected to the smoothing filter, and a voltage controlled oscillator 114 controlled by the voltage generated in the loop filter.
A specific circuit configuration of the phase comparator 121 is shown in FIG. 23.
An operation timing chart for the phase comparator 121 is shown in FIGS. 24 and 25.
FIG. 24 is an operation timing chart for the output signal 200 of the voltage controlled oscillator 114, the duty factor of which is smaller than 50%, and FIG. 25 is another timing chart for the output signal 200, the duty factor of which is larger than 50%.
The T.sub.C signal becomes "H" state at the leading edge of an input pulse signal 100, and becomes "L" state at the trailing edge of the next-arriving output signal 200. At the same time, the T.sub.S signal becomes "H" state at the same edge and is reduced to "L" state at the leading edge of the output signal 200. At the same time, the T.sub.D signal becomes "H" state at the same edge, and is reduced to "L" state at the trailing edge of the output signal 200.
The difference between the pulse width of the T.sub.C signal and that of the T.sub.D signal makes up the phase difference between the input pulse signal 100 and the output signal 200.
The smoothing filter 112 converts the phase difference into a voltage, holds the voltage at timing Ts, and applies a current proportional to the voltage to the loop filter 113. FIG. 26 shows the output characteristic of the smoothing filter 112.
The loop filter 113 includes a resistor R.sub.F and a capacitor C.sub.F. A loop filter having a different configuration may be used with equal effect. The current produced from the smoothing filter 112 is converted into a voltage at the loop filter 113, and controls the voltage-controlled oscillator 114 thereby to change the frequency of the output signal 200 thereof. The operation of the phase sync circuit makes it possible for the phase of the output signal to coincide with that of the input pulse signal 100.